Signal Integrity

Curtiss Wright Controls Defense Solutions has over 2 decades of experience in high performance backplane design and simulation, having performed Signal Integrity analysis and design of numerous custom switch fabric backplane designs. Our personnel have experience in performing full 3D modeling and simulation of interconnects at frequencies up to 20 GHz.
 


Today’s high performance systems require world class signal integrity capabilities. Many of today’s standard switched fabric backplanes are operating at 2.5 Gbaud to 3.125 Gbaud, with leading edge products operating at 6.25 Gbaud to >10 Gbaud. Examples of these higher speeds are Gen2 PCIe at 5 Gbaud, Gen2 SRIO at 6.25 Gbaud, and Ethernet 10GBASE-KR at 10.3 Gbaud.

VPX Interconnect Eye Diagrams Without (left) and With (right) Equalization at 10.3 Gbaud

Signal Integrity - 1

In fact, we have performed signal integrity 
simulation studies for standard groups in developing many of today’s standard backplanes. In applications ranging from PICMG 2.16 to MicroTCA, VXS, VPX, or custom backplanes, Curtiss Wright Controls Defense Solutions is the vendor of choice for high-speed backplane signaling.

  • Simulated Eye-diagrams allow evaluation of the channel's net ability to transmit data

  • Simulated TDR and TDT are also available for investigating discontinuities in the signal path
  • 
Frequency domain analysis including calculated parameters for 1000BASE-KX, 10GBASE-KX4, 10GBASE-KR and VITA 68 compliance

  • Statistical analysis including bathtub curves for BER


We have the industry's leading signal integrity analysis tools:

  • 
HFSS 3D field solver

  • ADS frequency domain and statistical analysis 

  • HSPICE time domain analysis
  • 
Curtiss Wright Controls Defense Solutions post processing algorithms
 


Curtiss Wright Controls Defense Solutions has developed an advanced signal integrity analysis methodology and post-processing to support 
10GBASE-KR running at 10.3 Gbaud per pair. This is based on frequency domain analysis and post processing of several channel parameters as defined in IEEE 802.3-2008. Time domain analysis (eye diagrams) as well as statistical “StatEye-like” analysis of BER are also included. 
This methodology is needed for upcoming higher speed serial standards. We have performed a study of 10.3Gbaud Ethernet 10GBASE-KR 
on VPX backplanes – see the complete tech paper in the white paper section of the website. 
The VITA 68 VPX Compliance Channel draft also proposes to adopt this methodology to define channel characteristics for multiple fabric types.

VPX Interconnect Insertion Loss (IL) and Insertion Loss to Crosstalk Ratio (ICR) for operation at 10.3 Gbaud

Signal Integrity Chart 2