CHAMP-WB/VPX6-474 6U OpenVPX Virtex-7

CHAMP-WB/VPX6-474 6U OpenVPX Virtex-7

The CHAMP-WB is the first entry in Curtiss-Wright Defense Solutions’ family of user-programmable Xilinx Virtex-7 FPGA-based computing products, designed to meet the needs of challenging embedded high-performance digital signal and image processing applications. The CHAMP-WB is targeted specifically at wide-band, low latency applications that require large FPGA processing, wide input/output requirements, with minimal latency. When combined with the TADF-4300 module, featuring 12 GS/s 8-bit ADC technology and 12 GS/s 10-bit DAC technology from Tektronix, an extremely high performance wide-band DRFM system can be created with is 3 times the capability of any COTS vendor. The combined card-set is called the CHAMP-WB-DRFM.

The CHAMP-WB couples the dense processing resources of a single large Xilinx Virtex-7 FPGA with two high-bandwidth mezzanine sites on a rugged 6U OpenVPX (VITA 65) form factor module. The CHAMP-WB complements this processing capability with a data plane directly connected to the FPGA with support for Gen2 Serial RapidIO® (SRIO). 10.3 Gbps Aurora links can also be supported between FPGA cards. Alternate fabrics can also be supported with different FPGA cores. A Gen3 PCI Express (PCIe) switch connected to the Expansion Plane provides a way for a single host card, such as the VPX6-1957 or CHAMP-AV8, to control multiple CHAMP-WB cards without utilizing dataplane bandwidth. Two 64-bit 4GB DDR3L memory banks provide 8 GB of on-card data capture or pattern generation capability. An auxiliary x4 SERDES link and 16 LVDS pairs provide additional I/O capability. The two mezzanine sites support standard FMCs and have an additional connector to provide enhanced bandwidth and capability. The extra connector provides at least another 48 differential pairs each as well as extra clocking, power and control signals. Running up to 600 MHz DDR, there is support for over 19GB/s of data I/O on each mezzanine site. Additional clocking and synchronization signals have been routed to the backplane to provide additional flexibility. Furthermore, one of the FMC sites has an option to take up to eight of the backplane SERDES and rout them to the mezzanine site to support new JESD204B serial I/O FMCs or Serial FMCs.

  • ŠOpenVPX™ (VITA 65) profile MOD6-PAY-4F1Q2U2T-12.2.1-11, VPX REDI (VITA 48 option)
  • ŠŠSingle user-programmable Xilinx Virtex-7 FPGAs (X690T or X980T), with
    • 8 GB DDR3L SDRAM in two banks
    • Four 4-lane serial data plane links to the backplane (support up to 10.3 Gbps data rates)
      • Gen2 SRIO or alternate fabrics with different FPGA cores
    • One 4-lane Gen3 PCIe connection to a Gen3 PCIe switch
    • One additional x4 10.3 Gbps link to the backplane
    • 16 LVDS pairs to the backplane
    • Two enhanced FMC interfaces with 128+ differential signal pairs
      • One site supports JESD204B or Serial FMCs with up to 8 serial links
        • The other site has optional support for up to 160 LVDS pairs with X690T FPGA
  • ŠŠTwo Mezzanine sites with support for FMC (VITA 57) or enhanced FMC
  • ŠŠOnboard PCIe Gen3 switch - Two 8-lane expansion plane fabric ports to the backplane with configurable NTB support
  • Sensors for monitoring board power consumption
  • ŠŠSupport for ChipScope Pro and JTAG processor debug interfaces
  • ŠŠBackplane clock/sync paths to mezzanines sites
  • ŠŠFXTools BSP and FPGA design kit with highly-optimized IP Blocks, development environment, reference designs, scriptable simulation test benches and software libraries VxWorks and Linux variants available
  • VITA 48 1” pitch format
  • Ruggedization levels
    • Air-cooled Level 0 (commercial)
    • Conduction-cooled Level 200 (future)
  • ŠŠPath to variant with Processor (contact factory)
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